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Technical Lead I - VLSI

UST · Posted today

  • Bengaluru, Karnataka, India (On-site)
  • Full-time
  • 8+ yrs

About the role

Role Description

  • Must have a solid understanding of SoC verification flows and experience with SoC verification in multiple clients.
  • Should be an independent learner with experience in developing C-based tests for ARC/ARM/RISC-based SoCs.
  • Must be an individual contributor capable of managing other CWs.
  • Requires a good understanding of SV, UVM test benches, and experience with protocols such as APB, AXI, I2C, UART, PCIe, or DDR.
  • Should be able to take the SoC verification test bench and port it for FPGA RTL verification and maintain the test bench for FPGA-RTL.
  • Must possess strong debugging skills in SoC Verification.
  • Candidates should have 8+ years of relevant experience.
  • Candidates should have 5-8 years of relevant experience.

Skills

vlsi design,soc design,systemverilog,asic design,

Skills

vlsi designsoc designsystemverilogasic design
Technical Lead I - VLSI at UST, Bengaluru, Karnataka, India (On-site) | Quark9